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1 fnxxxx may 17, 2012 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012 . all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are t he property of their respective owners. t e c h e l l w lcd video processor with built-in decoder, triple adcs, lvds & ttl inputs, mcu, osd, tcon and lvds panel interface TW8836 the TW8836 is a highly inte grated lcd video processor that incorporates many of the features required to create a multi-purpose lcd display system into a single package. this includes a high quality 2d comb ntsc/pal/secam video decode r, triple high speed rgb adcs, an lvds and ttl digital input interface, high quality scaler and de-interlace r, as well as a versitile osd, high performance mcu, and lvds or ttl output panel interface. the TW8836 can support input resolutions up to 1080p and can drive lcd panels at resolutions up 1366 x 768. the TW8836s video processing capability incl udes arbitrary h/v scaling, panoramic scaling, image mirroring, image adjustment and enhancement, black and white stretch, etc. the feature set and versatility of this device makes it an ideal solution for in-car lcd di splay applications, as well as portable display applications such as pico projectors. applications in-car display pico projector & portable media player portable dvd and dvr players analog video decoder ntsc (m, 4.43) and pal (b, d, g, h, i, m, n, n combination), pal (60), secam with automatic format detection three 10-bit adcs and analog clamping circuit. fully programmable stat ic gain or automatic gain control for the y or cvbs channel programmable white peak con trol for the y or cvbs channel software selectable analog inputs allows composite, s-video, analog ypbpr or rgb high quality adaptive 2d comb filter for both ntsc and pal inputs pal delay line for color phase error correction image enhancement with 2d dynamic peaking / cti. digital sub-carrier pll for accurate color decoding programmable hue, brightne ss, saturation, contrast, sharpness selectable differ ential or single-ended cvbs input digital horizontal pll and advanced synchronization processing for vcr pl ayback and weak signal performance high quality horizontal and ve rtical filtered down scaling with arbitrary scale down ratio up to 2ch differential or 4ch single ended cvbs input analog rgb inputs triple high speed 10-bit adcs with clamping and programmable gain amplifier sog and h/v sync support fo r ypbpr or rgb input built-in line locked pll with sync separator supports input resolution up to 1080p digital inputs support supports both bt656 and 601 video formats supports ycbcr/rgb 24-bit inpu t (bi-directional) up to 1080p resolution single channel lvds input up to 720p resolution supports rgb 565 + bt 656 at the same time tft panel support built-in programmable timing controller supports 3, 4, 6 or 8 bits per pixel up to 16.8 million colors with built-in dithering engine supports digital panels (t tl) or single channel lvds panels up to wxga (13 66 x 768) resolution, 85mhz supports serial (8 -bit) rgb panel font based on screen display eight window font osd with bordering / shadow 10kb programmable font ram and 512 display ram 1/2/3/4 bits/pixel supports variable width (12/16), height (2~32) spi flash based on screen display 9 bitmap based osd windows in 2 layers through spi with alpha blending between layers supports 4/6/8 bits/pixel supports rle decompression for two windows ? nalog nalog ga ga ? gcl gcl ? w w h, i, m h, i, th au h a m, n m n s s sup su igita igit a ta ta port p or e l e s inpu s i np u lock lo c ? syn syn cke ck e ? ain a ain csu csu ? 0-bit 0-bit n am n am pu p bit a it a ? uts uts adcs dc
TW8836 2 image processing high quality scaler with both up/down and panorama / water-glass scaling support built-in 2d de-interlacing function programmable brightness, contrast, saturation, hue and sharpness programmable color transient improvement control supports programmable cropping of input video and graphics independent rgb gain and offset controls dtv hue adjustment programmable 8-bit gamma co rrection for each color black/white stretch clock generation spread spectrum profile based on triangular modulation with center spread programmable modulation fr equency and spread width timing controller (tcon) supports programmable inte rface signals for control column (source) driver/row (gate) driver mcu industry standard 8052 based code fetch from exter nal spi flash memory 256b code cache 2k xdata memory supports power save mode with 32k internal clock isp (in system programming) through i2c supports 24-bit addressing bt.656 output independent itu-r 656 compatible ycbcr(4:2:2) output format supports progressive itu-r 656 output format for both interlaced and progressive inputs itu-r 656 output generated from decoder, argb, drgb and post scaling path touch screen controller built-in 4-wire resistive touch screen 12Cbit adc 4 channel auxiliary input miscellaneous supports fast mode pl us i2c interface up to 4 pwms gpios 1.8/3.3v internal operation 1.8v i/o support power-down mode single 27mhz crystal 128-pin lqfp and 144 pin tfbga package ? ing ing ng g ? g) thr ) th ? h 3 h 3 hro ro 2k i ki ory ory ? ? ? ?
TW8836 3 table of contents analog video decoder ........................................................................... 1 analog rgb inputs................................................................................. 1 digital inputs support ............................................................................ 1 tft panel support .................................................................................. 1 font based on screen display ............................................................ 1 spi flash based on screen display ................................................... 1 image process ing ................................................................................... 2 clock generation .................................................................................... 2 timing controller (tcon) ..................................................................... 2 mcu ........................................................................................................... 2 bt.656 output .......................................................................................... 2 touch screen controller ....................................................................... 2 miscellaneous .......................................................................................... 2 table of contents ............................................................................... 3 ordering information .......................................................................... 4 TW8836 functional bl ock diagram................................................... 4 functional description ....................................................................... 5 overview ................................................................................................... 5 analog front-e nd .................................................................................... 5 video decoder ......................................................................................... 5 sync processor .................................................................................... 5 horizontal sync processing ................................................................ 5 vertical sync processing ..................................................................... 5 color decoding ..................................................................................... 6 y/c separat ion ..................................................................................... 6 color demodulation ............................................................................. 6 automatic chroma gain control ......................................................... 6 low color detection and removal ..................................................... 6 automatic standard detection ............................................................ 6 video format support .......................................................................... 7 component proces sing ....................................................................... 7 luminance processing ........................................................................ 7 the hue and saturation ...................................................................... 7 touch screen controller ....................................................................... 7 digital input support .............................................................................. 7 lvds video input interface ................................................................. 8 input image control .............................................................................. 10 image scaling ........................................................................................ 10 image enhancement processing ...................................................... 10 black/white stretch ............................................................................ 10 tft panel support ................................................................................ 10 dithering .............................................................................................. 10 gamma table .................................................................................... 10 tcon .................................................................................................. 10 lvds out put format........................................................................... 10 lvds color mapping ......................................................................... 11 font based on screen display .......................................................... 12 on chip osd functions ..................................................................... 12 basic register setting flow example for built-in osd controller.. 13 osd window start location: built-in osd controller ..................... 15 osd_ram configuration .................................................................... 15 alpha blending for osd window ..................................................... 16 alpha blending concept .................................................................... 16 spi flash on screen display.............................................................. 17 pixel order .......................................................................................... 20 rlc data format ............................................................................... 21 osd display path .............................................................................. 22 built-in microcontroller ........................................................................ 24 TW8836 mcu block diagram ............................................................. 25 microcontroller interface ..................................................................... 25 two wire serial bus interface ........................................................... 26 pin diagram ......................................................................................29 TW8836 128 pin lqfp (top-vie w) ................................................ 29 pin descriptions (tba) .....................................................................30 package outline drawing 1 .............................................................31 q128.14x14: 128 lead low plastic quad flatpack package (lqfp) 0.4mm pitch.............................................................................. 31 package outline drawi ng 2 .............................................................32 v144.7x7a : 144 lead thin, fine pitch plastic ball grid array package (tfbga) rev 0, 1/11 ............................................................ 32 top view .......................................................................................... 32 bottom view ................................................................................. 32 parametric information .....................................................................33 ac/dc electrical parameters.............................................................. 33 filter curves .....................................................................................39 anti-alias filter ..................................................................................... 39 decimation filter ................................................................................. 39 chroma band pass filter curves ..................................................... 40 luma notch filter curve for ntsc and pal .................................. 40 chrominance low-pass filter curve ............................................... 41 TW8836 register summary (tba) ...............................................42 life support policy ...........................................................................43 revision history ...............................................................................43 ? ? ? ........... .......... ......... ... ... ... ............... ............ .... .... .............. .......... ........ . ... . ......... ..... ............. ....... .. ...... ... ... ............ .. 10 1 ....... ....... 1 1 7 7 ... ... 7 . 8 . 8 0 para pa b b aram r am acka ck top top bo bo 44.7 44.7 ckage kage p p utline utline x7a : 1 x7a : 1 mm p mm p e dr ed ? 28 l 28 l 128 le 28 le m pitch pitc ? ) ) ..... ..... wing 1 wing ad ? fp (t fp (t .... ... e ...... .... (top top ? ce ce . ........... .. p-vie v
TW8836 4 ordering information p p a r t n u m b e r p p a r t m m a r k i n g p a c k a g e ( p b - f r e e ) p k g . d w g . # TW8836-ba1-cr (note e r r o r ! r e f e r e n c e s o u r c e n o t f o u n d . ) TW8836 ba1-cr 144 ball tfbga (7mmx7mm) v144.7x7a TW8836-la1-cr (note e r r o r ! r e f e r e n c e s o u r c e n o t f o u n d . ) TW8836 la1-cr 128 lead lqfp (14mmx14mm) q128.14x14 TW8836at-la1-gr (note e r r o r ! r e f e r e n c e s o u r c e n o t f o u n d . ) TW8836at la1-gr 128 lead lqfp (14mmx14mm) q128.14x14 notes: 1. these intersil pb-free plastic packa ged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requ irements of ipc/jedec j std-020. 2. these intersil pb-free wlcsp and bg a packaged products employ special pb-f ree material sets; molding compounds/die attach materials and snagcu - e1 solder ball terminals, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free wl csp and bga packaged products are ms l classified at pb-free peak reflow temperatures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. ? ? ? s of i of d p d p f ipc/ ipc/ r r produ prod /j /j pec p rohs rohs du u ecial p cial p c sl sl pb pb h is h is assifi assifi al s al is ro s r o ? sets, sets oh ? ? ? ? ? ?
TW8836 5 TW8836 functional block diagram functional description overview intersil|techwells TW8836 lcd vide o processor is a highly integr ated tft panel controller. it integrates a high quality 2d comb ntsc/pal/secam video decoder, scalers and de-inter lacer, timing controller, fl exible osd (font based and spi bit-map based osd engine), and a high performance mcu. this unique level of mixe d signal integration turns a tft panel into a flexible display system. TW8836 incorporates easy-to-op erate features in a single pac kage for multi-purpose in-car lcd display, portable dvd and dvrs, me dia players, and pico projectors. it contains all the logic required to convert analog or digital video signals in various formats to the signal formats that are ne cessary to drive various kinds of tft panels. it supports different panel re solutions depending on the scaler and panel clock settings, and has a built-in tcon for direct connecting with l ow cost tcon-less panel. the integrated analog front -end contains adcs with clamping circ uits and automatic gain control (agc) circuits as well as anti-aliasing filters to minimize the external component coun t. the built-in video decoder employs proprietary 2d comb filter y/c sepa ration technologies to produce exce ptionally high quality pictures. the chip's internal logic synchronizes the panel frame rate to the incoming inpu t frame rate. a high quality image-scaling engine is used to convert the diff erent input resolution formats to the output panel resolution. an inte rnal de-interlacing engine also allows interlaced video to be displayed. in addition, TW8836 has an array of integrated value-added featur es and input/output flexibility that makes it an extremely versitile si ngle chip solution. on screen display (osd) is supported through an on-chip multi-window osd engine for maximum flexibilit y. integraged 12-bit adcs for 4-wire resistiv e touch screen control, single channel lvds (open ldi) input and output, as well as an on-chip mcu are just a few of these features. the host control interface supports a standard 2-wire serial bus ? ), ), an an m. tw m. t ? deo deo nd nd a a ? vid vid eo de eo d eo p eo p n n n n
TW8836 6 analog front-end the analog front-end converts analog video signals to the required digit al format. each channel contains an automatic clamping circuit, agc circuit, anti-aliasing filter and high perfor mance adcs to minimize the number of external components needed. the clamping circuit restores the signal dc le vel so it can be properly digitized. the analog inputs source selections are software programmab le. different input source s have different signal condit ioning logic to properly convert the signal into correct format for further processing. video decoder the decoder sync processor of the vide o input detects horizontal synchronization and vertic al synchronization signals in the composite video or in the y signal of an s-video input. the processor contains a digital phase-locked-loop (pll) and decision logic to achieve reliable sync detection in both stable signals as well as in unst able signals, such as those from vcr fast forward or rewind. horizontal sync processing horizontal synchronization pr ocessing contains a sync separator, a phase-lo cked-loop (pll), and the related decision logic. the horizontal pll loc ks onto the extracted horizontal sync in all cond itions to provide a jitter free output image. from there, the pll also provides ort hogonal sampling raster for the down-stream pro cessor. it has a very wide lock-in range for tracking any non-standard video signal. vertical sync processing the vertical sync separator detects the vertical synchr onization pattern in the inpu t video signals. a detection window controls the sync determination to provide a more reliabl e synchronization and simulates the functionality of a pll without the complexity of a pll. the field st atus is determined at the vertical synchronization time based on the vertical and horizontal sync relationship. color decoding y/c separation the color-decoding block c ontains the luma / chroma separation engine for composite video signals and multi-standard color demodulation. for ntsc and pal stand ard signals, the luma / chroma separation c an be done either by comb filter or notch/band-pass filter combinati on. for secam standard signals, only notch/band-p ass filter is available. the default selection for ntsc/pal is comb filter. the characteri stics of the band-pass filter can be found in the filter curve section. in the case of comb filter, the decode r separates luma (y) and chroma (c) of a ntsc/pal composite video signal using a proprietary adaptive comb filter algor ithm. it leads to good y/c separation with mi nimal cross luma and cross color at both horizontal and vertical edges. due to the nature of the line buffer used in the comb filter, there is always a two line processing delay in the output images regardless of what standard or filter option is chosen. color demodulation the color demodulation for ntsc and pal standards are done by quadrature mi xing of the chroma signal to the base band and extracting the chroma components with the low-pass filt er. the low-pass filter char acteristics can be selected for optimized transient color pe rformance. for the pal system, the pal id or th e burst phase switching is identified to aid the pal color demodulation. the secam color demodulation process consists of bell filtering, fm demodulation, and de-emphasis filtering. the chroma carrier frequency is identified in the proce ss and used to control th e secam color demodulation. the sub-carrier signal used in the color demodulator is generated by a direct di gital synthesis pll that locks onto the input sub-carrier reference (color burst). this arrangeme nt allows any sub-standard ntsc or pal signal to be demodulated easily. automatic chroma gain control the automatic chroma gain control (acc) compensates for reduced amplitudes ca used by transmission loss in the video signal. in the ntsc/pal standards, the color reference signal is the burst on the ba ck porch. this color-burst amplitude is ? al edg al edg put im ut i ? r al r al dges. ges ? od o d algor algo er. t er. t er s r s . for s for s the ch the c / / andard andard sec sec / chrom / chro rd s s m d d at d at hron ro at the tth te te oniza oniz ern in ern i n a a p proce roce ov ov ovid ovi ocess ces ? ea ea ? pll pl ll), ll), ? ), and an
TW8836 7 calculated and compared to standard ampli tude. the chroma (cx) signals amplitude is then compensated accordingly. the range of acc control is C6db to +24db. low color detection and removal for low color amplitude signals, bl ack and white video, or very noisy signals, the color will be killed. the color killer use s the burst amplitude measurement to switc h-off the color when the measured bu rst amplitude falls below a programmed threshold. the threshold has programmed hysteresis to preven t oscillation of the color kille r operation. this function can be disabled by programming a low threshold value. automatic standard detection the video decoder has automatic standard di scrimination circuitry. the circuit uses burst-phase, burst-frequency, and frame rate to identify ntsc, pal or seca m color signals. the standards t hat can be identified are ntsc (m), ntsc (4.43), pal (b, d, g, h, i), pal (m), pal (n), pal (60) and secam (m). any of these standards can be included or excluded in the standard recognition process by software c ontrol. the identified standard is indi cated by the standar d selection (sdt) register. automatic standar d detection can be overridden by softw are controlled standard selection. video format support the integrated video decoder supports all common video formats as shown in table 1. this needs to be programmed appropriately for each of the composite video input formats. table 1. video input formats supported format ntsc-m 525 60 3.58 mhz u.s., many others ntsc-japan (1) 525 60 3.58 mhz japan pal-b, g, n 625 50 4.43 mhz many pal-d 625 50 4.43 mhz china pal-h 625 50 4.43 mhz belgium pal-i 625 50 4.43 mhz great britain, others pal-m 525 60 3.58 mhz brazil pal-cn 625 50 3.58 mhz argentina secam 625 50 4.406mhz 4.250mhz france, eastern europe, middle east, russia pal-60 525 60 4.43 mhz china ntsc (4.43) 525 60 4.43 mhz transcoding notes: (1). ntsc-japan has 0 ire setup. ? ? ? ? ? ? ? ? ? 6 ? 525 525 ? ? 5 5 ? ? 5 5 ? ? ? ? ? ? ? ? ? f ? 6 6 ? ? ? ? le 1 le 1 . lds vide vide ? ? ? deo deo format forma form for m m m ? ? ? ?
TW8836 8 component processing luminance processing the video decoder adjusts brightness by adding a programmable value (in regist er brightness) to the y signal. it adjusts the picture contrast by changing the gain (in register contrast) of the y signal. the decoder also provides a sharpness c ontrol function through a control regist er. the center frequency of the peaking filter is selectable, and a coring function is provided along with the sharpne ss control to reduce enhancement to the noise. the hue and saturation when decoding ntsc signals, the decoder can adjust the hue of the chroma si gnal. the hue is defined as a phase shift of the subcarrier with respect to the burst. this phase sh ift can be programmed thro ugh a control register. the color saturation can be adjusted by changing the gain of cb and cr signals for all ntsc, pal and secam formats. the cb and cr gain can be adjusted independently for flexibility. touch screen controller built-in 12-bit adc touch screen controller in TW8836 provide s accurate position reading with simplified digital operation and can also be used to monitor up to four auxiliary inputs with touch interrupt. digital input support in addition to analog inputs, TW8836 also has dual digital inputs for ycbcr/rgb data and a single channel lvds port (open ldi type). the dtv input supports up to 24 bit digital rgb with resolution up to 1080p and opperates independently from the lvds input. the d tv port is bi-directional, and can be used as a digital output port to provide duplicate secondary panel output. lvds video input interface TW8836 lvds video input interface takes 4 channel-data lvds inputs and one lvds cl ock input. the 4 channel serial input data are de-muxed intol parallel 28bits output (24bits of rgb and 4 bi ts of hsync, vsync, dataready, and cntl). lvds data ch0 lvds data ch1 lvds data ch2 lvds data ch3 lvds clock lvds to parallel pll red[7:0] grn[7:0] blu[7:0] hsync vsync drdy cntl clk figure 1 lvds rx functional block ? ? l l v v ? d d d a a t t a a c h h 0 0 ? utp ut nnel-d nel-d tput (24 put (2 -data data onal na w al, an l, a with r with and nd r ycb r yc b hres res cbcr bcr t. . re re ? adin adin ? ?
TW8836 9 the pll recovers clock fr om vlds input and generates synchronized capture clock for 24 video data. the following figure shows the lvds rx data / clock timing diagram for seral and parallel data. rxin0[6] rxin0[5] rxin0[4] rxin0[3] rxin0[2] rxin0[1] rxin0[0] rxin0[1] rxin0[0] rxin0[6] rxin0[5] rxin0[4] rxin0[3] rxin0[2] rxin0[1] rxin0[0] clkinp/clkinn rxin0p/rxin0n rxin0[6] rxin0[5] rxin0[4] rxin0[3] rxin0[2] rxin0[1] rxin0[0] current cycle previous cycle next cycle rxout[6:0] current cycle previous cycle next cycle clk_byte tdc figure 2 lvds rx data/clock input/output timing diagram ? ? ? m ng dia ng dia ag ? ? ? ? ? ? ?
TW8836 10 in order for TW8836 lvds rx to operate properly, the input data switching timing needs to met. figure 3 and table 2 illustrates TW8836 lvds rx strobl e data timing parameters. current cycle previous cycle tclk rxin0 rxin1 rxin2 rxin3 rspos0_min rspos0_max rspos1_min rspos1_max rspos2_min rspos2_max rspos3_min rsp os 3 _ max rspos4_min rspos4_max rspos5_m in rspos5_max rspos6_min rspos6_max symbol parameters min typ max units rspos0 input strobe position for bit 0 0.49 0.84 1.19 ns rspos1 input strobe position for bit 1 2.17 2.52 2.87 ns rspos2 input strobe position for bit 2 3.85 4.21 4.55 ns rspos3 input strobe position for bit 3 5.53 5.88 6.23 ns rspos4 input strobe position for bit 4 7.21 7.56 7.91 ns rspos5 input strobe position for bit 5 8.89 9.24 9.59 ns rspos6 input strobe position for bit 6 10.57 10.92 11.27 ns figure 3 lvds input strobe position table 2 lvds rx switching timing (f=85mhz) ? ? fi f ? ? ? r ? p o s 6 _ ? s p o s 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
TW8836 11 input image control the input cropping control provides a way for programming the active display window region for the selected input video or graphic. in normal operation, the fi rst active line starts with the vsync sign al. this and the vertical active length register setting are used to determine the active vertical window. the active pi xel starts hsync. this and the horizontal active width register are used to de termine the active horizontal window. the vertical window is programmed in line increments. the horizontal window is programmed in single pixel increments for single pixel inpu t mode or two pixel increments for double pixel input mode. if the data qualifier is used, then only qua lified pixels will be counted in the window size. image scaling the internal high quality image-scaling engi ne operates in several modes. the firs t is the bypass mode. no image scaling is done in this mode. the number of acti ve output lines per frame and the number of active output pixels per line are identical to the input active lines and pixels, respectively. this mode is best used for displaying computer graphics at the panel's native resolution. by default, the input active window is zoome d up to the full screen for display. this is used for non-interlaced data like pc graphics or progressive scan video. the vertical and horizontal magnification rati o can be adjusted independently. TW8836 has an option called frame-sync mode which does not use a frame buffer. in this mode, the zoom ratio and output clock rate should be coordinated appr opriately to avoid internal buffer overrun. the TW8836 has a built-in 2d de-interlacing engine to proce ss interlaced video inputs. when used, every input field is zoomed to the full output frame resolution. the de-interlaced fields can also be proper ly adjusted to have fields aligned correctly to avoid any artifacts. the offset can be programmed to provide maximum flexibility. the horizontal scaler can be pr ogrammed to perform non-linear scaling : p anorama scaling for displaying 4:3 input on a 16:9 display and water-glass scaling for displaying 16:9 input on a 4:3 display. image enhancement processing black/white stretch this feature is to expand the dynamic range of the in put image, which creates a more vivid image impression. tft panel support TW8836 supports a variety of active matr ix tft panel types and resolutions up to 1366x768 including panels with a ttl or single channel lvds interface. dithering TW8836 has a dithering circuit to reduce the output dynamic range to fit the panel type. this allows lcd panels with 3, 4, 6 or 8 bits per color per pixel to displa y up to 16.8 million colors and lcd panels wi th 3 bits per color per pixel can display up to 2.1 million colors. both spati al and frame modulation dithering are ava ilable. when dithering with the least significant 4-bits of input data it uses spatial modulation with 4x4 blocks of pixels. when dith ering with the least significant 1 to 3 bits of input data, it uses either spatial modulation with 2x2 pixel blocks, or frame modulation. gamma table TW8836 has an integrated gamma table for each color outpu t and is fully programmable through the host bus. tcon the integrated timing controller supp orts flexible column/row driver control signals to in terface with tcon-less panel directly. lvds out put format TW8836 is able to control the output order for panel control signals vs, hs and de by register settings. ? cu cu xel to d xel to hsp sp ? t to r t to odis odis ? ored re atrix atrix ix tft x tft e inp e inp nput im nput i m 4 4 ng 4:3 di 4:3 di g : pa g : pa is i e m e m pan an be be axim axim in i e pro e p r ? nput npu o ? un. n. ? this m this m be ad e ad sm m ? for fo adjust adju mod od
TW8836 12 lvds color mapping TW8836 is able to control the output color order.
TW8836 13 font based on screen display the TW8836 has a built-in osd contr oller with programmable ram font. the osd di splay is independent of the input active window settings and the scaling ratio. the on-chip osd controller is a characte r-based controller. the pre-defined charac ter or graphic bit map is stored in the font ram. it can store up to 379 single c olor fonts when the character is 12 pixels wide by 18 pi xels high. the characters can be displayed on the screen in four user defined window locations of any size from 1 to 512 characters. the spaces between characters are also programmable . there is a limit of 512 characters that may be di splayed on screen at one time in all windows combined. the attribut es of each window can also be set to give it a shadow effect or 3-d effect. in addition, the characters can be expanded by a factor of 2, 3 or 4 in vertical or horizontal dire ctions and have the blinking effect and border/shadow effect on a character by character basis. on chip osd functions font sram: max 379 (12x18) user progr ammable single color font (10240x8 sram) character register sram : 512 loca tion (9-bit font address + 10- bit character attribute, 512x19 sram) characters character color: 16 colors character background color: 16 colors character blinking: enable/disab le, 1 hz blinking frequency character border/shadow effect: enable/disable ( m u l t i o s d w i n d o w d i s p l a y c a s e : c h i p h a s a l i m i t a t i o n ) character space: both h and v pr ogrammable by number of pixels quick character change in window: programma ble start address and buffer size programmable osd color palette support re-designed osd font supporting standar d alpha-numerical character set windows number of windows: 4 independent windows window color: 16 colors window zoom: 2, 3, 4 times zoom by do t number, h/v separate zooming control window position: programmable h direction: 1-pixel per step, v direction: 1-line per step window size: both h and v program mable by number of characters window bordering/shadowing effect : 4 in dependent windows enable/disable control window alpha blending contro l : 4 independent windows control 16 different color for alpha blending support(4-bit control) window 3-d effect : 4 independ ent windows enabl e/disable control window border color : 16 colors window border width: programmable ? er wid er wi ? or or width: dth ? i i r : 16 r : 1 or alp or al p ndepe de p ing ing ontrol : ontrol pha pha ogram ogra g effec g effec :4 4 pixel p p ixe amma amma t dot l per l p er ot numb ot num s s ha-n a a-num -nu um um art a art er of er of t add t add n n ? ) ) ? of pix of pix ) ) ? ? ? ?
TW8836 14 basic register setting flow exam ple for built-in osd controller step_1: osd_font_size_configuration 1. select font width to be 12 or 16 - 0x300 (bit4) 2. set font height - 0x350 (bit4-0) 3. set sub-font total count - 0x351 (bit6-0) step_2: osd_window_config uration setting for w w i n d o w # 1 (0x310~0x31f) note) w w i n d o w # 2 (0x320~0x32f), w w i n d o w # 3 (0x330~0x33f), w w i n d o w # 4 (0x340~0x34f) 1. osd window disable 0x310, bit7 2. osd window zoom multiplier 0x310, bit1-0: v, bit3-2:h 3. osd window background b color 0x31e, bit6-4 4. osd window background g color 0x31e, bit6-4 5. osd window background r color 0x31e, bit6-4 6. osd window background color extension 0x31e, bit7 7 osd window 3-d ef fect top/bottom mode select 0x31b, bit6 8. osd window 3-d effect level select 0x31b, bit5 9. osd window 3- d effect enable/disable 0x31b, bit7 10. osd window h-start loca tion (see details in next page) 0x313, bit7-0 0x312, bit6-4 11. osd window v-start loca tion (see details in next page) 0x314, bit7-0 0x312, bit1-0 12. osd window width 0x316, bit5-0 13. osd window height 0x315, bit5-0 14. osd window border_line width 0x318, bit4-0 15. osd window border_line b color 0x317, bit2-0 16. osd window border_line g color 0x317, bit2-0 17. osd window border_line r color 0x317, bit2-0 18. osd window border_line enable 0x318, bit7 19. osd window border color extension 0x317, bit3 20. osd window shadow width 0x31c, bit4-0 21. osd window shadow b color 0x31b, bit2-0 22. osd window shadow g color 0x31b, bit2-0 23. osd window shadow r color 0x31b, bit2-0 24. osd window shadow enable 0x31c, bit7 25. osd window shadow color extension 0x31b, bit3 26. osd window h-space width (between border_line and characters) 0x319, bit6-0 27. osd window v-space width (between border_line and characters) 0x31a, bit6-0 28. character h-space width (between character and character) 0x31d, bit7-4 0x31c, bit6 29. character v-space width (between character and character) 0x31d, bit3-0 0x31c, bit5 30. osd window alpha blending color select 0x352, bit4-0 31. osd window alpha blending value control 0x311, bit3-0 32. window content start address 0x305, bit0 0x306, bit7-0 33. repeat 1 C 32 ? th (b h (b ? idth (b idth ( ? ? ? ? (betw betw ? xten xten ? ? ensio nsio ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? ? ? ? ? 0 0 0 0 31 3 0x312 0x312 31 31 ? 13, b 13, 2 2 ? b b b, bit , bit bit b it ? ? t5 5 ? ? ? ? ? ? ? ?
TW8836 15 step_3: osd_color_attribute / font setting (osd ram) 1. enable osd ram access - 0x304 (bit0 = 0) 2. set multi-color start address - 0x305 (bit3-1), 0x30b (bit7 -0), 0x353 (bit7-0) , 0x354 (bit7-0) 3. osd ram address - 0x305 (bit0), 0x306 (bit7-0) - the first address is step_1_ 32 window content start address. 4. osd ram data port high (font address) - 0x307 data is written to above address automatically. - 0x304 (bit5=0) select lower 256 char. (bit5=1) select upper 256 char. 5. osd ram data port bit18 (border effect ), bit17 (blinking effect ), bit16 (upper|lower 256 char.) - 0x304 bit4, bit7, and bit5 data are written to above address automatically. 6. osd ram data port lo w (color attribute) - 0x308 data is written to above address automatically. 7. repeat 3), 4), 5), and 6) - the address should be increased by one each. step_4: color look-up table setting 1. select color look-up table write address - 0x30c (bit[5:0]) - bit[5:0]: these 6 bits sp ecify one of the 64 entries in the look-up ta ble. each entry is a 16-bit rgb color by its content. - there are 65536 colors available. for single color font, only sixteen of them are accessible by osd controller at a given time. 2. color look-up table control bits setting - 0x30d (high byte), 0x30e (low byte) - the data of the look-up table is accessed through 0 x30d and 0x30e. 3. repeat 1) and 2) to program each entry of the look-up table. step_5: font_ram_data setting (font ram) 1. enable font ram access - 0x304 (bit0 = 1) 2. font ram address setting - 8 bits(h00 C hff) -0x309 - h00~hff : single font ram(256 pr ogrammable characters) 3. font ram data port - - 0x30a data is written to above address automatically. 4. repeat (4) at 27 times for one font ram data - the internal address automatic ally increases by one each. 5. new font ram address setting C 8 bits 6. repeat 3), 4), 5) - the font ram address should be increased by one each. note) as for the font ram configuration and font bit mapping, see the detailed description step_6: end of osd setting and enable osd 1. osd on/off enable control 0: on, 1: off - 0x30c (bit6 = 0) 2. osd window enable - 0x310 (bit7 = 1) window1 enable ? data data 0 a d a d ? : si : si a por a po ? singl sing ) ) settin setti s s ing - ing ram) ram m) m) ry of t ry of cesse ess he he sed t sed t or fo or f font font in t in he loo he loo ? ? ? ?
TW8836 16 osd window start location: built-in osd controller internal generated osd de position de layed from h-sync: 0x303[7:0] osd window h_start location from start of internal osd de: 0x312[6:4], 0x313[7:0] in crement by 1 pixel at a time osd window v_start location from start of vact: 0x312[1:0] , 0x314[7:0] increment by 1 line at a time 0 1 2 0 18 address the characters can be displa yed on the screen in four user defined window locations of any size from 1 to 512 characters. there is a limit of 512 characters that may be displayed on screen at one time in all windows combined. example window #1: address 0 C 2 (3 character) window #2: address 3 C 100 (98 character) window #3: address 101C 254 (154 character) window #4: address 255 - 511 (257 character) osd_ram configuration 50 510 511 18 0 8 7 fontaddress (11-bits) bit 18: border/shadow bit 17: blinking bit 16: up256 bit 15 - 8: font address fontattribute (8-bits) bit 7: characters background color extension bit 6: characters background r bit 5: characters background g bit 4: characters background b bit 3: characters color extension bit 2: character r bit 1: character g bit 0: character b ? shado hado ? ( ( 1 1 1 1 ? 1 1 1 1 - - b b ? ? ? ? ? 1 (2 1 ( 1 (257 (2 5 ? 54 54 154 c 54 57 57 ? er) er) aracte ract ? ) ?
TW8836 17 alpha blending for osd window the TW8836 uses "alpha blending" in osd 4 separation window s & 64 separation colors. the upper 32 separation colors are forced to 0. alpha blen ding mixes (adds) the video signal and osd signal at the following specified levels. in other words, alpha blending determin es the transparency of the osd window each color to in relation to video signal. when alpha blending is disabled, the only osd data is displayed in osd window. the alpha blending level selection ar e 4-bit assigned, it can suppor t 8 different level controls. the alpha blending level bits are in register 0x311[ 3:0] for window#1, 0x321[3:0] for window#2, 0x331[3:0] for window#3, 0x341[3:0] for window#4 and alpha blending color selecti on bits are in register 0x352[4:0] for 32 separation colors. a a l p h a [ 3 : 0 ] v v i d e o l e v e l 0000 0.00 0001 12.5 0010 25.0 0011 37.5 0100 50.0 0101 62.5 0110 75.0 0111 87.5 1000 100 alpha blending concept x + video level osd data video data x 1 C video level ? o dat o da ? ? ? ? level le e l ? ? ? ?
TW8836 18 spi flash on screen display the TW8836 spiosd provides flexible mapping between its di splay on the lcd and its bit mapped image stored in the spi memory. there are total nine windo ws provided. one of the windows is of complex type, the rest are of simple type. there are two layers of sp iosd that can be alpha blended with ea ch other and the active video. in general, a buffer in the spi memory is allocated for the image to be displayed. the simple type refers to the windows that have the same buffer size and disp lay size. whereas the buffer size of a complex window is usually larger than the display size. the spiosd window #0 is designated as complex window. the other eight windows (s piosd window #1 ~ #8) are simple windows. the bit mapped image stored can be 4, 6 or 8 bits per pixel. during display, the pixel is fetched from the spi memory and mapped to a 32-bit real color pixel by the lut (look up table). this 32-bit real color pixel consists of 24-bit rgb, 7-bit alpha blending attribute, and one bit blinking attribute. the re al color pixel is then mixe d with video before displaying on the lcd panel. to reduce the storage size and the access time, rlc (run length code) decode ci rcuitry is provided. however, only one of the eight simple windows can be assigned to receive rlc pixel data. the other windows must receive uncompressed pixel data. each of the nine windows has its own set of register but shares a common 512 entry lu t. for each window, lut entry offset register is provide d for flexible mapping. all nine windows can be active and ove rlapped at the same time without blending among themselves. blending with video can be pixel ba sed or window based. looping control for adjacent buffers is provided for the complex window. animat ion can be achieved by properly allocating multiple buffers in the adjacent area and the looping control. s s p i o s d w i n d o w d i s p l a y s t a r t i n g l o c a t i o n a n d s i z e s there are four registers used to specify t he staring location and size on the lcd: w i n d o w i h o r i z o n t a l s t a r t w i n d o w i v e r t i c a l s t a r t w i n d o w i h o r i z o n t a l l e n g t h w i n d o w i v e r t i c a l l e n g t h lcd display window i v start window i h start window i v length window i h length ? lc lc ? lcd dis cd di s tarin tari ring l i ng l e e s s s ol. ow l. . ow. a ow. a nim i ding in ? ng am g a ? ? lut. f lut. f fo fo ? re
TW8836 19 s s p i o s d w i n d o w b u f f e r m e m o r y two (or three for complex window) registers define the buffer starting lo cation and boundaries: w i n d o w i b u f f e r m e m o r y s t a r t i n g a d d r e s s w i n d o w i b u f f e r m e m o r y h o r i z o n t a l l e n g t h w i n d o w i b u f f e r m e m o r y v e r t i c a l l e n g t h (complex window only) for complex window two additional registers point to the starting locat ion of the image stored: w i n d o w i i m a g e v e r t i c a l s t a r t (complex window only) w i n d o w i i m a g e h o r i z o n t a l s t a r t (complex window only) w i n d o w i b u f f e r m e m o r y h o r i z o n t a l l e n g t h w i n d o w i i m a g e v s t a r t w i n d o w i i m a g e h s t a r t w i n d o w i b u f f e r m e m o r y s t a r t i n g a d d r e s s [ 2 3 : 0 ] w i n d o w i h l e n g t h w i n d o w i v l e n g t h w i n d o w i b u f f e r m e m o r y v e r t i c a l l e n g t h ? ? ? h h u ? h h ? o o ? r r ? i i ? z z ? o o ? u u ? f f ? f f f f ? e e ? r ? o o ? n n ? t t ? a a ? ? ? ? ? ? ? ? ? ? ? i ? ? ? ? ? ?
TW8836 20 s s p i o s d w i n d o w l o o p c o n t r o l for complex window, three registers are used for loop control: w i n d o w i l o o p i n g h o r i z o n t a l f r a m e n u m b e r (complex window only) w i n d o w i l o o p i n g v e r t i c a l f r a m e n u m b e r (complex window only) w i n d o w i f r a m e d u r a t i o n (complex window only) in the diagram below, the l l o o p i n g h o r i z o n t a l f r a m e n u m b e r register contains a value n, and the l l o o p i n g v e r t i c a l f r a m e n u m b e r register contains a value m. the display starts from frame #00 and then moves horizontally to the right and then vertically down. the display order is #00, #01, #02, #0n, #10, #11, #12, #1n, . #m0, #m1, #mn. each fr ame stays on for t he time specified by f f r a m e d u r a t i o n register. w i n d o w i b u f f e r m e m o r y h o r i z o n t a l l e n g t h w i n d o w i i m a g e v s t a r t w i n d o w i i m a g e h s t a r t w i n d o w i b u f f e r m e m o r y s t a r t i n g a d d r e s s [ 2 3 : 0 ] w i n d o w i b u f f e r m e m o r y v e r t i c a l l e n g t h w i n d o w i b u f f e r m e m o r y h o r i z o n t a l l e n g t h b u f f e r # 0 0 w i n d o w i b u f f e r m e m o r y h o r i z o n t a l l e n g t h w i n d o w i i m a g e v s t a r t w i n d o w i i m a g e h s t a r t w i n d o w i b u f f e r m e m o r y h o r i z o n t a l l e n g t h b u f f e r # 0 1 w i n d o w i b u f f e r m e m o r y h o r i z o n t a l l e n g t h w i n d o w i i m a g e v s t a r t w i n d o w i i m a g e h s t a r t w i n d o w i b u f f e r m e m o r y h o r i z o n t a l l e n g t h b u f f e r # 0 n w i n d o w i i m a g e v s t a r t w i n d o w i i m a g e h s t a r t w i n d o w i b u f f e r m e m o r y v e r t i c a l l e n g t h b u f f e r # 1 0 w i n d o w i i m a g e v s t a r t w i n d o w i i m a g e h s t a r t w i n d o w i b u f f e r m e m o r y v e r t i c a l l e n g t h b u f f e r # m 0 w i n d o w i i m a g e v s t a r t w i n d o w i i m a g e h s t a r t b u f f e r # m n f r a m e # 0 0 f r a m e # 0 1 f r a m e # 1 0 f r a m e # 0 n f r a m e # m 0 f r a m e # m n ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 ? e ? ? ? ? ? ? ? ? ? ? ? ? ? m ? e ? ? ? ? ? ? ? ? ? ? ? ? ? ?
TW8836 21 pixel order pixel data (uncompressed) stored in spi memory foll ows little endian order. the following diagram shows the pixel on lcd display and its corresponding storage order in the spi memory for pixel width 4, 6 and 8 bit wide. p 0 0 p 0 1 p 0 2 p 0 3 p 0 1 7 6 5 4 3 2 1 0 p 0 0 p 0 2 p 0 3 p 1 0 p 1 1 p 1 2 p 1 3 p 1 1 p 1 0 p 1 2 p 1 3 p 0 0 p 0 1 p 0 1 p 0 2 p 0 2 p 0 3 p 1 0 p 1 0 p 1 1 p 1 1 p 1 2 p 1 3 7 6 5 4 3 2 1 0 p 0 0 p 0 2 p 0 1 p 0 3 a a + 1 a + 2 p 1 0 p 1 2 p 1 1 p 1 3 7 6 5 4 3 2 1 0 4 b i t 6 b i t 8 b i t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
TW8836 22 rlc data format rlc data format is shown below: t: type to follow, 0 for data, 1 for cnt data: uncompressed data cnt: repeat count the width of data and cnt are set by rlc control register. the valid data width is 4, 6, or 8. the width of cnt can be 2 up to 16. the diagrams below show original data sequence of d0, d1, d2, d3, d4, and d5 before and after compression. in this example the data width is 8 and the cnt width is 4. data d2, d3, and d4 are the same. original data: rlc compression result: rlc data stored in memory: t d a t a / c n t t d a t a / c n t t d a t a / c n t t d a t a / c n t d 0 d 1 d 2 d 3 d 4 d 5 0 d 0 0 d 1 0 d 2 2 1 0 d 5 d 0 0 0 d 0 d 1 0 d 1 d 2 1 d 2 2 d 5 0 d 5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d ? ? ? ? ? ? ? 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
TW8836 23 osd display path in normal mixing order, video input is mixed with font osd fi rst. the resultant output is then mixed with spiosd. alternatively, video inpu t can be mixed with spiosd first and then font osd. osd blending path #1 lut 512x32 addr data window 0 control window 1 ~ 8 control line buffer spiosd alpha blending video font osd alpha blending font osd osd + video spiosd pixel delineator rlc decoder spi dma interface lut 512x32 addr data window 0 control window 1 ~ 8 control line buffer spiosd alpha blending font osd alpha blending osd + video spiosd pixel delineator rlc decoder spi dma interface ? ? ? ? ? ? ? ? ? ? ? ft alpha t font p alpha ? s os ? ? ? ? ? ? ? ? ? ? ? ? ? ? l ? lin ? ? ? ? ? ? ? ? ? ? ? ? ?
TW8836 24 osd blending path #2 osd + video font osd alpha blending font osd video lut 512x32 addr data window 0 control window 1 ~ 8 control line buffer spiosd alpha blending spiosd pixel delineator rlc decoder spi dma interface ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
TW8836 25 built-in microcontroller TW8836 has built-in 8052 microcontroller with program ca che memory to enhance mcu performance. TW8836 mcu is 100% software compatible with industry st andard 8052 with additional add-on features and faster instruction execution time. t t h e m a i n f e a t u r e s o f t w 8 8 3 6 m c u industry standard 8052 core timer 0, 1 and timer 2 support 2 uarts up to 115200bps support external in terrupt in t0~int6 io port C most of digital p ins can be configured to gpio power save mode with internal 32khz watchdog t h e a d d i t i o n a l a d d - o n f e a t u r e s f o r t w 8 8 3 6 m c u program fetch from external spi flash with single/dual/quad mode 256 b code cache and 2k xdata memory additional timer 3 and timer 4 for 2 baud rate generator 8 extended interrupt units int7~int14 support ir receiver and irq output internal isp rom boot selection spi dma read/write xmem c o n t r o l r e g i s t e r f o r m c u o p e r a t i o n spi flash mode for mcu program fetch - 0x4c0 (bit2-0) spi clock control - 0x4e1 (bit5-4), - 0x4e1 (bit2-0) mcu cache enable C sfr 0x9b (bit0) mcu timer clock divider control - 0x4e2, - 0x4e3 for timer 0 - 0x4e4, - 0x4e5 for timer 1 - 0x4e6, - 0x4e7 for timer 2 - 0x4e8, - 0x4e9 for timer 3 - 0x4ea, - 0x4eb for timer 4 boot strap sequence TW8836 provides external boot se lect pin only for during device power up spi dma to mcu xmem 1.) set spi flash mode for dma operation - 0x4c0 (bit2-0) 2.) set spi dma length - {0x4da, 0x4c8, 0x4c9} 3.) set spi dma command - {0x4ca, 0x4cb, 0x4cc, 0x4cd, 0x4ce} 4.) set - 0x4c3 (bit7-6 = 2b11) select dma destination to mcu xmem 5.) set - 0x4c3 (bit5-4) dma access mode 6.) set - 0x4c4 (bit1) dma read/write mode 7.) set - 0x4c6 (bit3-0), - 0x4c7 (b it7-0) for destinat ion start address 8.) set - 0x4c4 (bit0 = 1) to start dma execution strap strap 6pr pr ? p se pse ? cont co - 0x 0x 0x9b (b x9b (b ntrol ntrol 4), - 0x 4), - 0 bit0 bit0 tch - ch - - 0x 0x ? ? ? e e ?
TW8836 26 TW8836 mcu block diagram microcontroller interface the host interface is accessed via 2-wire serial bus interface. it alwa ys operates as a slave device. spi flash spi interface cache xmem spi dma path mcu program data mcu xdata boot select cache enable isp rom mcu core mcu xmem embedded mcu block off-chip flash ? ? ? ? ? ? ? sp s s s ? i i ? p p xme xme ? ? ? ?
TW8836 27 two wire serial bus interface mc sda start condition stop condition mc_sclk mc_sclk device id (1-7) r/w index (1-8) data (1-8) mc_sda start condition stop condition ack ack ack re-start condition mc_sclk device id (1-7) r/w index (1-8) mc_sda ack ack data (1-8) stop condition nack start condition device id (1-7) r/w ack figure 4. definition of the serial bus interface bus start and stop figure 5. one complete register writ e sequence via the serial bus interface figure 6. one complete register read sequence via the serial bus interface ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? te r ? ? writ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
TW8836 28 the two wire serial bus interface is used to allow an external micro-controller to write control data to, and read control or other information from the internal registers. mc_sclk is the se rial clock and mc_sda is th e data line. both lines are pulled high by resistors connected to vdd. ics communicate on the bus by p ulling mc_sclk and mc_sda low through open drain outputs. in normal operation the master generates all clock pulses, but c ontrol of the mc_sda line alternates back and forth between the master and the slave. for both read and write, each byte is transferred msb first, and the data bit is valid whene ver mc_sclk is high. the device is operated as a bus slave de vice. the 7-bit device address field is fi xed and concatenated with the read/write control bit to form the first byte transfe rred during a new transfer. if the read/write control bit is high the next byte will be read from the slave device. if it is low the next byte will be a write to the slave. when a bus master (the host microprocessor) drives mc_sda from high to low, while mc_sclk is high, this is defined to be a st art condition (see figure 4). all slaves on the bus listen to determ ine when a start condition has been asserted. after a start condition, all slave devices lis ten for their device addresses. the host then sends a byte consisting of the 7- bit slave device id and the r/w bi t. this is shown in figure 5. (the next byte is normally the index to the internal registers and is a write to the device therefor e the first r/w bit is normally low.) after transmitting the device address and the r/w bit, the master mu st release the mc_sda line while holding mc_sclk low, and wait for an acknowledgeme nt from the slave. if the address matches the device address of a slave, the slave will respond by driving the mc_sda line low to acknowledge the condition. the mas ter will then continue with the next 8- bit transfer. if no device on the bus respon ds, the master transmits a stop conditi on and ends the cycle. notice that a successful transfer always includ es nine clock pulses. to write to the internal register, the master sends another 8-bit of data, it loads this to the register pointed by the interna l index register. the device will acknowledge the 8-bit data transfer and automaticall y increment the index in preparation for the next data. the master can do multi ple writes if they are in ascending se quential order. after each 8-bit transfer the device will acknowledge the receipt of the 8-bits with an acknowledgement pulse. to end all transfers, the host has to issue a stop condition. ? ? ? owle ow cend en wledg wle dg aut au nding ndin g it it utom utom oads t ads t on on ? ter w er w and and ? ice a ce a will will _sd _sd add add ? da lin da l dre r
TW8836 29 table 3. serial bus interface 7-bit slave address and read write bit serial bus interface 7-bit slave address 1 0 0 0 1 0 1 1=read 0=write the device read cycle has two phases. the fi rst phase is a write to the internal in dex register. the second phase is the read from the data register. (see figure 6). the host initiates the first phase by sending the start condition. it then sends the slave device id together with a 0 in the r/w bit position. the index is then sent followed by ei ther a stop condition or a second start condition. the second phase starts with the second start c ondition. the master then resends the same slave device id with a 1 in the r/w bit po sition to indicate a read . the slave will transfer the contents of the desired register. the master remains in control of the clock. after trans ferring eight bits, the slave releases and the master takes control of the mc_sda line and acknowledge the receipt of data to th e slave. to terminate the last transfer the master will issue a negative acknowledge (mc_ sda is left high during a clock pulse ) and issue a stop condition. g table 4. serial bus interface timing p a r a m e t e r s y m b o l m i n t y p m m a x u n i t s bus free time between stop and start t bf 740 - - ns mc_sda setup time t ssdat 74 - - n s mc_sda hold time t hsdat 50 - 900 ns setup time for start condition t ssta 370 - - ns setup time for stop condition t sstop 370 - - ns hold time for start condition t hsta 74 - - ns rise time for mc_sclk and mc_sda t r - - 300 ns serial bus interface timing g stop start stop start mc_sda mc_sclk t bf t hsta t sstop t ssta t ssdat t r t f t hsdat data ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 74 74 - ? 70 7 4 4 ? ? ? ? ? ? - - ? ? ? - - ? ? p p ? ? ? ? ? ?
TW8836 30 pin diagram TW8836 128 pin lqfp (top-view) ym/adc2 xm/adc1 yp/adc0 xp adc3 avdtsc avstsc vdd18 vss18 vd7/pwm3/gpioxx vd6/pwm4/gpioxx vd5/rxd1/gp ioxx vd4/txd1/gpioxx vd3/gpioxx vd2/gpioxx vd1/gpioxx vd0/gpioxx vdclk/gpioxx vddo vsso scl/p1.6 sda/p1.7 rstb fpb7/gpioxx fpb6/gpioxx fpb5/gpioxx fpb4/gpioxx fpb3/gpioxx fpb2/gpioxx fpg7/gpioxx fpg6/gpioxx fpg5/gpioxx avsad yin2- /cin1 cin0 y3/v1/yout yin2+/s og1/yin2 yin0- /yin1 yin0+/yin0 vin0 advad sog0 avspll avdpll vss18 vdd18 vdhs/ext_hs vdvs/ext_vs gpioxx/fpb7/dtv23 gpioxx/fpb6/dtv22 gpioxx/fpb5/dtv21 gpioxx/fpb4/dtv20 gpioxx/fpb3/dtv19 gpioxx/fpb2/dtv18 gpioxx/fpb1/dtv17 gpioxx/fpb0/dtv16 gpioxx/fpg7/dtv 15 gpioxx/fpg6/dtv14 gpioxx/fpg5/dtv13 gpioxx/fpg4/dtv12 gpioxx/fpg3/dtv11 gpioxx/fpg2/dtv10 gpioxx/fpg1/dtv9 gpioxx/fpg0/dtv8 fpg4/gpioxx fpg3/gpioxx fpg2/gpioxx fpr7/gpioxx fpr6/gpioxx fpr5/gpioxx fpr4/gpioxx fpr3/gpioxx fpr2/gpioxx tcpoln/gpioxx tcrev/gpioxx vdd33 vss33 fpr1/tclrl/lvtx0n fpr0/trclk/lvtx0p fpg1/tcudl/lvtx1n fpg0/tclp/lvtx1p fpb1/tcs pr/lvtx2n fpb0/trspb/lvtx2p fpde/troe/lvtxckn fphs/tcspl/lvtxckp fpvs/trspt/lvtx3n fpclk/tcclk/lvtx3p vdd33 mgpo p3.0/rxd0/gpioxx p3.1/txd0/gpioxx spid2 spid0 spiclk spid3 spics/(mcu_en) gpioxx/fpr7/dtv7 gpioxx/fpr6/dtv6 gpioxx/fpr5/dtv5 gpioxx/fpr4/dtv4 gpioxx/fpr3/dtv3 gpioxx/fpr2/dtv2 gpioxx/fpr1/dtv1 gpioxx/fpr0/dtv0 gpioxx/fphs/dtvhs gpioxx/fpvs/dtvvs gpioxx/fpclk/dtvclk xtali xtalo vss33 vdd33 gpioxx/lvrx0n gpioxx/lvrx0p gpioxx/lvrx1n gpio xx/lvrx1p gpioxx/lvrx2n gpioxx/lvrx2p gpioxx/lvrxclkn gpioxx/lvrxclkp gpioxx/lvrx3n gpioxx/lvrx3p vdd18 vss18 gpioxx/pwm1/int7/p1.0 gpioxx/pwm2/int8/p1.1 gpioxx/fpde/dtvde/int9/p1.2 gpioxx/dtvclk2/int10/p1.3 spiod1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 prelimiary subject to change ? ? ? s s sub ub pr p ? ? ? ?
TW8836 31 pin descriptions (tba) ? ? ? ? ? ? ?
TW8836 32 package outline drawing 1 q128.14x14: 128 lead low plastic quad flatpack package (lqfp) 0.4mm pitch
TW8836 33 package outline drawing 2 v144.7x7a : 144 lead thin, fine pitch plastic ball grid array pa ckage (tfbga) rev 0, 1/11 s s y m b o l m i l l i m e t e r m i n . n o m . m a x . a --- --- 1.20 a1 0.16 --- 0.26 m 0.53 ref. s 0.26 ref. b 0.27 0.30 0.37 e 0.50 basic d 6.90 7.00 7.10 d1 --- 5.50 --- e 6.90 7.00 7.10 e1 --- 5.50 --- note: 1. primary datum c and seating pl ane are defined by the spheri cal crowns of the solder balls. 2. dimension b is measured at the maximum sold er ball diameter, paralle l to primary datum c. 3. controlling dimension : millimeter . bottom view top view 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 2 d e e b 0 0 . 2 7 ~ 0 . 3 7 a 1 c o r n e r a 1 c o r n e r 0 0 . 1 5 m 0 0 . 0 5 c m c a b b 0 0 . 1 0 c 0 . 1 0 c // a e 1 d 1 c a a 1 s e a t i n g p p l a n e m a b c d e f g h j k l m 0 0 . 0 8 c s ? ? ? ? ? ? ? n ? e ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
TW8836 34 parametric information ac/dc electrical parameters table 5. absolute maximum ratings p p a r a m e t e r s y m b o l m i n t y p m a x u n i t s v dda18 (measured to v ssa18 ) 1.8v (note 1) vddam - - 1.98 v v dda33 (measured to v ssa33 ) 3.3v (note 1) vdda33m - - 3.6 v v dd18 (measured to v ss18 ) 1.8v (note 1) vdd18m - - 1.98 v v dd33 (measured to v ss33 ) 3.3v vdd33m - - 3.6 v voltage on any digital signal pin (see the note below) - v ss33 C 0.5 - 5.5 v analog input voltage (supplied by 1.8v) - v ssa18 C 0.5 - 1.98 v storage temperature t s C65 - +150 c junction temperature t j - - +125 c reflow soldering tpeak 255 +5/-0 (10~30 seconds) c note: 1. vdda18: avdad, avdpll vssa18: avsad, avspll v dda33 : avdtsc v ssa33 : avstsc v dd33 : vdd33 v ss33 vss33 v dd18 : vdd18 v ss18 : vss18 caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. this device employs high-impedance cmos devices on all signal p ins. it must be handled as an esd-sensitive device. voltage on a ny signal pin that exceeds the ranges list in table 5 can induce destructive latch-up. preliminary estimates subject to change ? ? ? uc n all s n all ctive latc ctive latc ll signal ll signa tch h ed for e ed for r exte ext e 55 +5 55 +5 ? +5/ +5 / ? ? ? ? ? ? ? ? - - ? - - ? ? ? ?
TW8836 35 p p a r a m e t e r s y m b o l m i n ( n o t e error! referen ce source not found. ) t y p m a x ( n o t e error! reference source not found.) ) u n i t s s u p p l y power supply io 3.3v v dd33 3.15 3.3 3.6 v power supply digital core 1.8v v dd18 1.62 1.8 1.98 v power supply analog 3.3v v dda33 3.15 3.3 3.6 v power supply analog 1.8v v dda18 1.62 1.8 1.98 v ambient operating temperature t a -40 - +105 c analog supply current 1.8v (cvbs) (component 1080p) (dtv 1080p) iaa18 - 38.2 - ma iaa18 189.3 ma iaa18 13 ma analog supply current 3.3v iaa33 - 3.6 - ma digital i/o supply current 3.3v (note e e r r o r ! r e f e r e n c e s o u r c e n o t f o u n d . ) idd33 - 30 - ma digital core supply current( note2) (cvbs, 27mhz) (cvbs, 108mhz) (component 1080p, 108mhz) (dtv 1080p, 108mhz) idd18 - 116 - ma idd18 - 141 - ma idd18 - 161 - ma idd18 - 146 - ma note: 1. compliance to datasheet limits is assured by one or more methods: prod uction test, characterization and/or design. 2. digital i/o and core power supply cu rrent measurement is base on wvga input (40mhz clock rate) with smpte pattern. ? ? ? er sup er su ts is ts is upply upply is assu is assu ? 108 10 8mh 08mhz 8mh z) z) mhz) mhz ) ? ? ? ? id id ? ? idd d idd d d ? dd18 d18 8 8 ? ? ? ? ? - ? ? ? ? ? ? ? ? 38 38 189 189 ? ? 8.2 8.2 ? ? ? ? ?
TW8836 36 p p a r a m e t e r s y m b o l m i n ( n o t e error! referen ce source not found. ) t y p m a x ( n o t e 1 ) u n i t s d i g i t a l i n p u t s input high voltage (ttl) v ih 2.0 - - v input low voltage (ttl) v il - - 0.8 v input high voltage (xti) v ih 2.0 - v dd33 + 0.5 v input low voltage (xti) v il - - 0.8 v input high current (v in = v dd ) i ih - - 10 a input low current (v in = vss) i il - - C10 a input capacitance (f = 1 mhz, v in = 2.4 v) c in - 5 - pf d i g i t a l o u t p u t s output high voltage (i oh = C4ma) v oh 2.4 - v dd33 v output low voltage (i ol = 4ma) v ol - 0.2 0.4 v 3-state current i oz - - 10 a output capacitance c o - 5 - pf note: 1. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. ? ? ? red by o ed by o ? one ? ? ? c c ? i i oz o c c ? oz oz ? ? ? ? ? ? ? 2.4 2. ? 4 4 ? ? ? ? ? ? ? ? - - ? ? ? ? ? ? ? ? ?
TW8836 37 p p a r a m e t e r s y m b o l m i n ( n o t e erro r! referen ce source not found. ) t y p m a x ( n o t e error! referenc e source not found.) ) u n i t s a n a l o g i n p u t analog pin input voltage vi - 1 - vpp yin0, yin1, yin2 and yin3 input range (ac coupling required) 0.5 1.0 2.0 vpp cin0, cin1 amplitude range (ac coupling required) 0.5 1.0 2.0 vpp vin0, vin1 amplitude range (ac coupling required) 0.5 1.0 2.0 vpp sog0, sog1 input range 0.02 0.3 1.8 v leds input range - - - v dcdcs - - - v analog pin input capacitance c a - 7 - pf a d c s adc resolution adcr - 9 - bits adc integral non-linearity ainl - 1 - lsb adc differential non-linearity adnl - 1 - lsb adc clock rate f adc - 27 60 mhz video bandwidth (-3db) bw - 9 - mhz note: 1. compliance to datash eet limits is assured by one or more methods: production test, characterization and/or design. ? b) b) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 5 5 ? ? ? ? 1.0 10 ? ? ? 0 0 ? ? ? ?
TW8836 38 p p a r a m e t e r s y m b o l m i n ( n o t e error! referen ce source not found. ) t y p m a x ( n o t e error! refere nce source not found.) ) u n i t s h o r i z o n t a l p p l l line frequency (50hz) f ln - 15.625 - khz line frequency (60hz) f ln - 15.734 - khz static deviation f h - - 6.2 % s u b c a r r i e r p l l subcarrier frequency (ntsc-m) f sc - 3579545 - hz subcarrier frequency (pal-bdghi) f sc - 4433619 - hz subcarrier frequency (pal-m) f sc - 3575612 - hz subcarrier frequency (pal-n) f sc - 3582056 - hz lock in range f h 450 - - hz c r y s t a l s p e c nominal frequency (fundamental) - 27 - mhz deviation - - 50 ppm load capacitance cl - 20 - pf series resistor rs - 80 - note: 1. compliance to datasheet limi ts is assured by one or more methods: prod uction test, characterization and/or design. 2. crystal deviation cro ssover normal operation temperature range. ? ? ? r norma norm a s ass s a al o l o assured sure ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 45 45 0 ? ? 3 3 3 ? ? ? ? 433 433 57 57 ? ? 3361 3361 ? 9545 954 ? 45 45 ? ? ? ? ? ?
TW8836 39 ? ? ? ? ? ? ?
TW8836 40 table 6. output timing p p a r a m e t e r s y m b o l t e s t c o n d i t i o n s m i n ( n o t e error! refere nce source not found.) ) t y p m a x ( n o t e error! referen ce source not found.) ) u n i t duty cycle fpclk fpclk div = 0 40% 50% 60% fpclk low time t1 fpclk = 9~80mhz 6.7 - 66.7 ns fpclk high time t2 fpclk = 9~80mhz 6.7 - 66.7 ns output hold time t3 fpclk div = 0, pol = low 6.0 - - ns fpclk div = 1, pol = low 9.0 - - ns fpclk div = 2, pol = high 21.0 - - ns fpclk div = 3, pol = low 34.5 - - ns output delay time t4 fpclk div = 0, pol = low - 10.5 14.5 ns fpclk div = 1, pol = low - 13.5 17.5 ns fpclk div = 2, pol = high - 25.5 29.5 ns fpclk div = 3, pol = low - 39.5 43.5 ns ? ? ? ? t ? t1 t1 t2 t2 ? ? ? ? ? ? fpc fp t t ? e ? c ? t ? e ? s ? ? ? ? ?
TW8836 41 note: 1. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. ? ? ? ? ? ? ?
TW8836 42 filter curves anti-alias filter decimation filter 0 2 4 6 8 10 12 x 10 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) magnitude response (db) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 x 10 7 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) gain (db) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ertz) ? ? ? .2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
TW8836 43 chroma band pass filter curves luma notch filter cu rve for ntsc and pal 0 1 2 3 4 5 6 7 8 9 x 10 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) magnitude response (db) pal/seam ntsc 0 1 2 3 4 5 6 7 8 x 10 6 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 frequency (hertz) gain (db) ntsc pal ? ? ? ? ? ? ? ? ? ? ? n ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
TW8836 44 chrominance low-pass filter curve low med high 0 1 2 3 4 5 6 x 10 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 frequency (hertz) gain (db) cbw=0 cbw=3 cbw=1 cbw=2 ? ? ? ? ? ert ? tz) ? ? ? 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ?
TW8836 45 TW8836 register summary (tba) ? ? ? ? ? ? ?
TW8836 all intersil u.s. products are manufactured, assemb led and tested utilizing iso9000 quality systems. intersil corporations quality certifications c an be viewed at www.intersil.com/design/quality. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be acc urate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor fo r any infringements of patents or other rights of third parties which may result from its use. no license is granted by impli cation or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil co rporation and its products, see www.intersil.com life support policy these products are not authorized for use as crit ical components in life supp ort devices or systems. revision history d d a t e r e v i s i o n c h a n g e april 2, 2012 0.3 initial preliminary version release may 17, 2012 0.4 updated block diagram and pin assignment june 29, 2012 0.5 insterted lvds rx information ? ? ? ? ? ? ?

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